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data sheet 1 STP2223BGA u2p upa to pci interface d escription the u2p * chip is the primary connection on an ultrasparc cpu board between the upa system bus (including ultrasparc processors and memory) and a pci based i/o subsystem. its major functions are upa port interface, pci bus interface, processor i/o data transfers, dma data transfers and interrupt dispatch. features ? full master and slave port connection to the high-speed ultrasparc upa interconnect architecture. the upa is a split address/data packet-switched bus which has a potential data throughput rate of over one gigabyte/sec. upa data is ecc protected. ? two physically separate pci bus segments, with full master and slave support. pci bus a has the following features: - 5 volt or 3.3 volt signalling. - 64-bit data bus. - compatible with the pci rev 2.1 speci?cation. - compatible with the pci 66mhz extensions. - support for up to four master devices (at 33mhz only). pci bus b has the following features: - 5 volt signalling. - 64-bit data bus. - compatible with the pci rev 2.1 speci?cation. - support for up to six master devices. ? two separate 16-entry streaming caches, one for each bus segment, for accelerating some kinds of pci dvma activity. single iommu with 16-entry tlb for mapping dvma addresses for both busses. ? a mondo-vector dispatch unit, or mdu, for delivering interrupt requests to ultrasparc cpu modules, including support for pci interrupts from up to six total slots, as well as interrupts from on board io devices. * u2p was code named psycho+ july 1997
2 STP2223BGA upa to pci interface u2p july 1997 p roduct s ummary the u2p uses the standard cell library from lucent technologies. it is implemented in 0.35 micron, 3 level metal and 3.3 volt optimized cmos technology. the u2p die has 352 signal pads (including specialty power/grounds) and 104 vss/vdd pads for a total pad count of 456. the u2p package is a 456 pin pbga, with 352 signal pins and 104 vss/vdd pins. its die con- sists of 170k gates and 29k bits of ram. the u2p design includes the following non-standard cells: ? 5v tolerant pci pads. ? 66mhz capable pci pads. ? upa pads (without holding amps). ? pll and pecl receiver for upa clock. ? pll for main clock. the upa operation is up to 100 mhz (10ns). its main internal clock is up to 66.7 mhz (15 ns). the pci bus a clocks at 1x or 0.5x internal clock (synchronous). the pci bus b clocks at 0.5x internal clock (synchronous). the maximum power consumption is 3 watts.
3 upa to pci interface u2p STP2223BGA july 1997 typical system partition figure 1. shows one possible con?guration of u2p in a pci ultrasparc system. u2p connects to the system controller chip and other upa ports via upa address, control and data busses. the system has both pci and epci slots, as well as an on board pci device (pcio). interrupt information is provided by the ric chip, and a jtag port is provided for board testing as well as in-circuit testing and debugging of u2p. figure 1. typical system block diagram ethernet ultra udb tag 512kb e$ clk ta(15:0) td(24+3+p) da(18+16be) d(128+16p) graphics upa/s 64b system memory simms memory address memory control memory data (256+32ecc) bmx upa_a0(35:0) upa_a1(35:0) upa_d0(127:0+ecc) upa_d1(63:0+ecc) upa_ctrl u2p upa interface pci interface a pci interface b pci bus pci bus ric controller sparc ebus 2 bus adapter pcio
4 STP2223BGA upa to pci interface u2p july 1997 external interfaces figure 2. summarizes the external interfaces and pins of u2p. figure 2. u2p external interfaces 64 2 7 4 4 4 8 2 64 8 7 6 6 2 64 8 36 6 5 5 3 2 6 u2p upa 130 pins test 10 pins intr. 6 pins clocks 5 pins pci a 96 pins pci b 96 pins 104 5 5 2 2 5 special pwr/gnd 8 pins 2 2 upa_databus upa_ecc upa_addressbus upa_arbitration upa_p_reply upa_p_reply upa_misc upa_reset_l upa_sys_clk jtag misc int_num tmr_clk psyclk bypass power/ground a_ad a_par a_c/be# a_ctrl a_req# a_gnt# a_idsel a_err a_clk pci_rst b_ad b_par b_c/be# b_ctrl b_req# b_gnt# b_err b_clk vssa vdda vdd5 shared pci rst 1 pin
5 upa to pci interface u2p STP2223BGA july 1997 block diagram figure 3. shows a conceptual block diagram of u2p. the actual implementation is somewhat different - for example, there are no internal bidirectional busses. block diagrams with the actual implementation details can be found in the u2p users manual. figure 3. u2p internal block diagram pci bus mondo pio ctl. upa dispatch unit bus ctl. timer/ counters ecc gen/ check dma ctl. pci bus b interrupts jtag upa pci bus streaming cache b pci bus a iommu streaming cache a merge buffer jtag module a module b
6 STP2223BGA upa to pci interface u2p july 1997 functional block overviews this section gives a brief description of each top level functional block. a more detailed description of each block can be found in the u2p users manual. each block is described in its own individual chapter in the u2p users manual. the top level blocks in u2p fall into one of ?ve categories: ?upa. ? pci. ? interrupt. ? internal control. ? miscellaneous. upa interface blocks the upa is ultrasparcs packet switched main system bus. in an ultrasparc system, the upa can operate up to 100 mhz. data and address have independent ?ow controls. each type of upa cycle (pio read, pio write, dma read, etc.) uses its own fifo-based queueing. there is a synchronization boundary between the upa interface blocks and other u2p blocks, which run at 66.7 mhz. ? upa master/slave : this block deals exclusively with upa address control. it listens to upa_a when u2p is a slave. it also arbitrates for and drives upa_a when u2p is a master. ? upa_reply: this block deals exclusively with upa data. it generates p_reply to the system controller (sc) asic during pio and copyback cycles. it also listens to s_reply from the sc and manages the upa data fifos accordingly. ? ecc generate: generates ecc on the outgoing 64-bit upa data path. ? ecc check: checks ecc on the incoming 64-bit upa data path. pci interface blocks ? pbm (pci bus module): this is the main portion of the pci interface. u2p contains two nearly identical copies of this block. one is designed to support a 64-bit pci bus at 66 mhz or 33 mhz with up to four master devices. the other supports a 64-bit pci bus at 33mhz with up to six master devices. the pbm adheres to all pci protocol guidelines as contained in the pci revision 2.1 speci?cation. each pbm controls arbitration, ?ow control and error handling for its bus segment. each pbm also handles the big- to little-endian byte twisting required for correct operation of both pio and dvma datapaths. ? iommu: for the portion of the pci memory address space which is reserved for dma to the upa bus, the iommu maps the pci address into the appropriate upa physical address. the iommu keeps the 16 most recently used translations in a tlb, and automatically performs hardware tablewalks on tlb misses. there is a single iommu supporting both pci busses. only a single translation can be in progress at a time, and during tablewalks, translations from the other bus segment will be delayed. ? streaming cache: the streaming cache (stc) is used to accelerate pci dma activity. for dma reads, the stc will speculatively prefetch 64-byte cache lines. for dma writes, the stc buffers up 64-byte lines before sending to the upa interface. there are two separate stc blocks in u2p, one associated with each pbm block. each stc contains storage for 16 virtual address tagged entries and their data, which is stored in 64-byte lines, allocated on a least recently used basis.
7 upa to pci interface u2p STP2223BGA july 1997 interrupt block mondo dispatch unit (mdu): in the sun-4u architecture, interrupts to a processor are sent as packets on the upa bus. the mdu in u2p is a system resource for generating such packets. the mdu accepts interrupt requests from the upa slave ports, pci busses and internal u2p sources and dispatches interrupt packets to the upa. internal control ? merge buffer: in order to allow sub-line writes into a 64-byte memory line, it is necessary to perform a read-modify-write operation on the upa. the merge buffer is responsible for generating the correct upa read, merging the partial line, and writing the whole block to the upa. ? pio control: decodes slave requests from the upa_a request fifo, arbitrates for the appropriate resource and dispatches the request. ? bus control: this is an internal arbiter shared by the pio control and dma control blocks. it schedules the use of the main internal data paths. ? dma control: arbitrates and decodes requests from internal dma sources (pbm, stc, iommu, mdu), and arbitrates for the appropriate upa fifo. miscellaneous ? timer/counter: contains two identical 32-bit timer-counters as speci?ed by the sun-4u architecture. used for system scheduling and pro?ling. ? jtag control: provides the necessary control for the standard ieee 1149.1 jtag port, as well as additional scan based features that are useful for debugging purposes. pci address map overview complete information on address maps and other software visible features of u2p can be found in the pro- grammers model chapter of the u2p users manual. a simpli?ed diagram showing pio and normal dvma address spaces is in figure 4.
8 STP2223BGA upa to pci interface u2p july 1997 figure 4. pio and dvma address spaces 0.0000.0000 1.0000.0000 pci b i/o space pci a i/o space pci a&b con?g space u2p internal regs 1.f000.0000 1.8000.0000 prom via pcio pci a mem space pci b mem space u2p upa unused pci b space dvma 0000.0000 xxx0.0000 8000.0000 pci bus a pci bus b u2p iommu upa address 0.0201.0000 0.0202.0000 unused 0.0100.0000 0.0200.0000 unused pci a space dvma 0000.0000 xxx0.0000 8000.0000 memory space memory space address space
9 upa to pci interface u2p STP2223BGA july 1997 s ignal d escription pin naming conventions ? active low signals are denoted by an underscore or underscore l, following the signal name, examples: b_cbe_[0] and upa_clk_l. ? direction is input (i), output (o), and bidirectional (io). pin summary table 1: signal name pre?xes functional block pre?x pci66 bus (66mhz) a_ pci bus (33mhz) b_ upa bus upa_ jtag port psy_t table 2: pin count section pins what it includes upa interface 130 upa master/slave/interrupter 64 bit interface pcia interface 97 66mhz, 64 bit pci interface, shared pci reset pcib interface 96 33mhz, 64 bit pci interface clock inputs 5 upa, u2p core, timer clocks and bypass miscellaneous 11 interrupts, reset, ext/int_event test 5 jtag port and diagnostics signal total 344 power/ground 112 including 8 special power/ground pins total 456
10 STP2223BGA upa to pci interface u2p july 1997 pinout by pin number table 3: pbga pinout signal name ball direction cell type description vdd a1 vss a2 ecc_vld a3 i bin02s upa ecc is valid upa_srly[2] a4 i bin02s upa system reply vdd a5 vss a6 upa_cr a7 i bin02s upa sc request upa_ap a8 io bn02z24s upa address parity upa_a[3] a9 io bn02z24s upa address vdd a10 vss a11 upa_a[14] a12 io bn02z24s upa address upa_a[19] a13 io bn02z24s upa address upa_a[24] a14 io bn02z24s upa address upa_a[29] a15 io bn02z24s upa address vss a16 vdd a17 int_num[4] a18 i b5in03s interrupt number boot_bus a19 i bin06s 1= boot device on pcib, 0= boot device on pcia pci_rst_ a20 o pci21mus pci reset vss a21 vdd a22 vdd5 a23 nvdd5p pcia input diode clamp reference voltage (note 1) a_ad[2] a24 io pcimxi21 pcia address/data bus vss a25 vdd a26 vss b1 upa_ecc[5] b2 io bn02z24s upa ecc bus upa_srly[0] b3 i bin02s upa system reply upa_srly[4] b4 i bin02s upa system reply upa_prly[1] b5 o boz24s upa port reply upa_prly[3] b6 o boz24s upa port reply upa_rin[0] b7 i bin02s upa request in upa_a[0] b8 io bn02z24s upa address upa_a[4] b9 io bn02z24s upa address
11 upa to pci interface u2p STP2223BGA july 1997 upa_a[8] b10 io bn02z24s upa address upa_a[11] b11 io bn02z24s upa address upa_a[15] b12 io bn02z24s upa address upa_a[20] b13 io bn02z24s upa address upa_a[23] b14 io bn02z24s upa address upa_a[28] b15 io bn02z24s upa address upa_a[32] b16 io bn02z24s upa address upa_rst_l b17 i pinx02s upa reset. main u2p reset. int_num[3] b18 i b5in03s interrupt number ext_event b19 io pnaxz24s external event interrupt int_event b20 o boz24s internal event interrupt upa_clk b21 i bied03s upa 100mhz input clock (pos, pecl) upa_bypass b22 i bin06na upa pll bypass psyclops_clk b23 i bin02na 66mhz main clock a_ad[1] b24 io pcimxi21 pcia address/data bus a_ad[3] b25 io pcimxi21 pcia address/data bus vss b26 upa_ecc[4] c1 io bn02z24s upa ecc bus upa_ecc[3] c2 io bn02z24s upa ecc bus upa_ecc[7] c3 io bn02z24s upa ecc bus upa_srly[1] c4 i bin02s upa system reply upa_dtst c5 i bin02s upa data stall upa_prly[2] c6 o boz24s upa port reply upa_arbrst_l c7 i bin02s upa arbitration reset upa_rin[2] c8 i bin02s upa request in upa_a[2] c9 io bn02z24s upa address upa_a[6] c10 io bn02z24s upa address upa_a[10] c11 io bn02z24s upa address upa_a[13] c12 io bn02z24s upa address upa_a[18] c13 io bn02z24s upa address upa_a[25] c14 io bn02z24s upa address upa_a[30] c15 io bn02z24s upa address upa_a[33] c16 io bn02z24s upa address int_num[1] c17 i b5in03s interrupt number int_num[5] c18 i b5in03s interrupt number psy_tms c19 i pina02s jtag test mode select vdda-va1 c20 nvddan pll 3.3v supply, ?ltered table 3: pbga pinout (continued) signal name ball direction cell type description
12 STP2223BGA upa to pci interface u2p july 1997 vssa-vs1 c21 nvssan pll ground vdda-va2 c22 nvddan pll 3.3v supply, ?ltered a_ad[0] c23 io pcimxi21 pcia address/data bus a_ad[6] c24 io pcimxi21 pcia address/data bus a_ad[8] c25 io pcimxi21 pcia address/data bus a_ad[7] c26 io pcimxi21 pcia address/data bus upa_ecc[1] d1 io bn02z24s upa ecc bus upa_db[63] d2 io bn02z24s upa data bus upa_ecc[2] d3 io bn02z24s upa ecc bus vss d4 upa_prly[0] d5 o boz24s upa port reply upa_prly[4] d6 o boz24s upa port reply upa_rin[1] d7 i bin02s upa request in upa_a[1] d8 io bn02z24s upa address upa_a[5] d9 io bn02z24s upa address upa_a[9] d10 io bn02z24s upa address upa_a[12] d11 io bn02z24s upa address upa_a[16] d12 io bn02z24s upa address upa_a[21] d13 io bn02z24s upa address upa_a[22] d14 io bn02z24s upa address upa_a[27] d15 io bn02z24s upa address upa_a[31] d16 io bn02z24s upa address upa_a[34] d17 io bn02z24s upa address int_num[2] d18 i b5in03s interrupt number vdd5 d19 nvdd5p 5v input diode clamp reference voltage (note 2) psy_trst_l d20 i pina02s jtag test reset upa_clk_l d21 i bied03s upa 100mhz input clock (neg, pecl) psy_bypass d22 i bin06na psyclk pll bypass vss d23 a_ad[9] d24 io pcimxi21 pcia address/data bus a_ad[12] d25 io pcimxi21 pcia address/data bus a_ad[10] d26 io pcimxi21 pcia address/data bus vdd e1 upa_db[60] e2 io bn02z24s upa data bus upa_db[62] e3 io bn02z24s upa data bus upa_db[61] e4 io bn02z24s upa data bus vdd e5 table 3: pbga pinout (continued) signal name ball direction cell type description
13 upa to pci interface u2p STP2223BGA july 1997 b_cpu_gnt_ e6 o boz24s pcib internal grant (debug only) vss e7 upa_srly[3] e8 i bin02s upa system reply upa_rout e9 o boz24s upa request out upa_av e10 io bn02z24s upa address valid vdd e11 upa_a[7] e12 io bn02z24s upa address upa_a[17] e13 io bn02z24s upa address upa_a[26] e14 io bn02z24s upa address int_num[0] e15 i b5in03s interrupt number vdd e16 psy_tclk e17 i bin02s jtag test clock psy_tdo e18 o b5oz10s jtag test data output psyclops_clkr e19 i refpad 66mhz clock reference pad to connect ext cap vss e20 a_ad[4] e21 io pcimxi21 pcia address/data bus vdd e22 a_ad[14] e23 io pcimxi21 pcia address/data bus a_ad[13] e24 io pcimxi21 pcia address/data bus a_ad[15] e25 io pcimxi21 pcia address/data bus vdd e26 vss f1 upa_db[58] f2 io bn02z24s upa data bus upa_db[59] f3 io bn02z24s upa data bus upa_db[57] f4 io bn02z24s upa data bus upa_ecc[6] f5 io bn02z24s upa ecc bus a_ad[5] f22 io pcimxi21 pcia address/data bus a_ad[18] f23 io pcimxi21 pcia address/data bus a_ad[16] f24 io pcimxi21 pcia address/data bus a_ad[17] f25 io pcimxi21 pcia address/data bus vss f26 upa_db[54] g1 io bn02z24s upa data bus upa_db[53] g2 io bn02z24s upa data bus upa_db[56] g3 io bn02z24s upa data bus upa_db[52] g4 io bn02z24s upa data bus vss g5 vss g22 table 3: pbga pinout (continued) signal name ball direction cell type description
14 STP2223BGA upa to pci interface u2p july 1997 a_ad[23] g23 io pcimxi21 pcia address/data bus a_ad[19] g24 io pcimxi21 pcia address/data bus a_ad[22] g25 io pcimxi21 pcia address/data bus a_ad[21] g26 io pcimxi21 pcia address/data bus upa_db[49] h1 io bn02z24s upa data bus upa_db[48] h2 io bn02z24s upa data bus upa_db[51] h3 io bn02z24s upa data bus upa_db[47] h4 io bn02z24s upa data bus upa_ecc[0] h5 io bn02z24s upa ecc bus a_ad[11] h22 io pcimxi21 pcia address/data bus a_ad[28] h23 io pcimxi21 pcia address/data bus a_ad[24] h24 io pcimxi21 pcia address/data bus a_ad[27] h25 io pcimxi21 pcia address/data bus a_ad[26] h26 io pcimxi21 pcia address/data bus upa_db[45] j1 io bn02z24s upa data bus upa_db[44] j2 io bn02z24s upa data bus upa_db[46] j3 io bn02z24s upa data bus upa_db[43] j4 io bn02z24s upa data bus upa_db[55] j5 io bn02z24s upa data bus a_ad[20] j22 io pcimxi21 pcia address/data bus a_ad[32] j23 io pcimxi21 pcia address/data bus a_ad[29] j24 io pcimxi21 pcia address/data bus a_ad[31] j25 io pcimxi21 pcia address/data bus a_ad[30] j26 io pcimxi21 pcia address/data bus vdd k1 upa_db[40] k2 io bn02z24s upa data bus upa_db[42] k3 io bn02z24s upa data bus upa_db[39] k4 io bn02z24s upa data bus upa_db[50] k5 io bn02z24s upa data bus a_ad[25] k22 io pcimxi21 pcia address/data bus a_ad[36] k23 io pcimxi21 pcia address/data bus a_ad[33] k24 io pcimxi21 pcia address/data bus a_ad[35] k25 io pcimxi21 pcia address/data bus vdd k26 vss l1 upa_db[37] l2 io bn02z24s upa data bus upa_db[38] l3 io bn02z24s upa data bus table 3: pbga pinout (continued) signal name ball direction cell type description
15 upa to pci interface u2p STP2223BGA july 1997 upa_db[36] l4 io bn02z24s upa data bus vdd l5 vss l11 vss l12 vss l13 vss l14 vss l15 vss l16 vdd l22 a_ad[39] l23 io pcimxi21 pcia address/data bus a_ad[37] l24 io pcimxi21 pcia address/data bus a_ad[38] l25 io pcimxi21 pcia address/data bus vss l26 upa_db[34] m1 io bn02z24s upa data bus upa_db[33] m2 io bn02z24s upa data bus upa_db[35] m3 io bn02z24s upa data bus upa_db[32] m4 io bn02z24s upa data bus upa_db[41] m5 io bn02z24s upa data bus vss m11 vss m12 vss m13 vss m14 vss m15 vss m16 a_ad[34] m22 io pcimxi21 pcia address/data bus a_ad[43] m23 io pcimxi21 pcia address/data bus a_ad[40] m24 io pcimxi21 pcia address/data bus a_ad[42] m25 io pcimxi21 pcia address/data bus a_ad[41] m26 io pcimxi21 pcia address/data bus upa_db[29] n1 io bn02z24s upa data bus upa_db[28] n2 io bn02z24s upa data bus upa_db[30] n3 io bn02z24s upa data bus upa_db[27] n4 io bn02z24s upa data bus upa_db[31] n5 io bn02z24s upa data bus vss n11 vss n12 vss n13 table 3: pbga pinout (continued) signal name ball direction cell type description
16 STP2223BGA upa to pci interface u2p july 1997 vss n14 vss n15 vss n16 a_ad[44] n22 io pcimxi21 pcia address/data bus a_ad[48] n23 io pcimxi21 pcia address/data bus a_ad[45] n24 io pcimxi21 pcia address/data bus a_ad[47] n25 io pcimxi21 pcia address/data bus a_ad[46] n26 io pcimxi21 pcia address/data bus upa_db[24] p1 io bn02z24s upa data bus upa_db[25] p2 io bn02z24s upa data bus upa_db[23] p3 io bn02z24s upa data bus upa_db[26] p4 io bn02z24s upa data bus upa_db[22] p5 io bn02z24s upa data bus vss p11 vss p12 vss p13 vss p14 vss p15 vss p16 a_ad[53] p22 io pcimxi21 pcia address/data bus a_ad[49] p23 io pcimxi21 pcia address/data bus a_ad[52] p24 io pcimxi21 pcia address/data bus a_ad[50] p25 io pcimxi21 pcia address/data bus a_ad[51] p26 io pcimxi21 pcia address/data bus upa_db[19] r1 io bn02z24s upa data bus upa_db[20] r2 io bn02z24s upa data bus upa_db[18] r3 io bn02z24s upa data bus upa_db[21] r4 io bn02z24s upa data bus upa_db[12] r5 io bn02z24s upa data bus vss r11 vss r12 vss r13 vss r14 vss r15 vss r16 a_ad[63] r22 io pcimxi21 pcia address/data bus a_ad[54] r23 io pcimxi21 pcia address/data bus table 3: pbga pinout (continued) signal name ball direction cell type description
17 upa to pci interface u2p STP2223BGA july 1997 a_ad[57] r24 io pcimxi21 pcia address/data bus a_ad[55] r25 io pcimxi21 pcia address/data bus a_ad[56] r26 io pcimxi21 pcia address/data bus vss t1 upa_db[16] t2 io bn02z24s upa data bus upa_db[15] t3 io bn02z24s upa data bus upa_db[17] t4 io bn02z24s upa data bus vdd t5 vss t11 vss t12 vss t13 vss t14 vss t15 vss t16 vdd t22 a_ad[58] t23 io pcimxi21 pcia address/data bus a_ad[60] t24 io pcimxi21 pcia address/data bus a_ad[59] t25 io pcimxi21 pcia address/data bus vss t26 vdd u1 upa_db[13] u2 io bn02z24s upa data bus upa_db[11] u3 io bn02z24s upa data bus upa_db[14] u4 io bn02z24s upa data bus upa_db[3] u5 io bn02z24s upa data bus vdd5 u22 nvdd5p pcia input diode clamp reference voltage (note 1) a_ad[61] u23 io pcimxi21 pcia address/data bus a_cbe_[0] u24 io pcimxi21 pcia command/byte enable bus a_ad[62] u25 io pcimxi21 pcia address/data bus vdd u26 upa_db[8] v1 io bn02z24s upa data bus upa_db[9] v2 io bn02z24s upa data bus upa_db[7] v3 io bn02z24s upa data bus upa_db[10] v4 io bn02z24s upa data bus vdd5 v5 nvdd5p 5v input diode clamp reference voltage (note 2) a_ack64_ v22 io pcimxi21 pcia 64bit ack a_cbe_[1] v23 io pcimxi21 pcia command/byte enable bus a_cbe_[4] v24 io pcimxi21 pcia command/byte enable bus table 3: pbga pinout (continued) signal name ball direction cell type description
18 STP2223BGA upa to pci interface u2p july 1997 a_cbe_[2] v25 io pcimxi21 pcia command/byte enable bus a_cbe_[3] v26 io pcimxi21 pcia command/byte enable bus upa_db[4] w1 io bn02z24s upa data bus upa_db[5] w2 io bn02z24s upa data bus upa_db[2] w3 io bn02z24s upa data bus upa_db[6] w4 io bn02z24s upa data bus b_ad[56] w5 io pci21lus pcib address/data bus a_idsel[3] w22 o pci21mun pcia con?g cycle chip selects a_cbe_[5] w23 io pcimxi21 pcia command/byte enable bus a_par w24 io pcimxi21 pcia ad[31:0]/cbe[3:0] even parity a_cbe_[6] w25 io pcimxi21 pcia command/byte enable bus a_cbe_[7] w26 io pcimxi21 pcia command/byte enable bus tmr_clk y1 i b5in03n 10mhz timer input clock upa_db[0] y2 io bn02z24s upa data bus b_cpu_req_ y3 o pci21lus pcib internal request (debug only) upa_db[1] y4 io bn02z24s upa data bus vss y5 vss y22 a_par64 y23 io pcimxi21 pcia ad[63:32]/cbe[7:4] even parity a_trdy_ y24 io pcimxi21 pcia target ready a_frame_ y25 io pcimxi21 pcia frame a_req64_ y26 io pcimxi21 pcia 64 bit request vss aa1 b_ad[62] aa2 io pci21lus pcib address/data bus b_ad[61] aa3 io pci21lus pcib address/data bus b_ad[63] aa4 io pci21lus pcib address/data bus b_ad[50] aa5 io pci21lus pcib address/data bus a_req_[0] aa22 i pci21min pcia bus request a_irdy_ aa23 io pcimxi21 pcia initiator ready a_stop_ aa24 io pcimxi21 pcia stop psy_tdi aa25 i pina02n jtag test data in vss aa26 vdd ab1 b_ad[60] ab2 io pci21lus pcib address/data bus b_ad[58] ab3 io pci21lus pcib address/data bus b_ad[59] ab4 io pci21lus pcib address/data bus vdd ab5 table 3: pbga pinout (continued) signal name ball direction cell type description
19 upa to pci interface u2p STP2223BGA july 1997 b_ad[49] ab6 io pci21lus pcib address/data bus vss ab7 b_ad[43] ab8 io pci21lus pcib address/data bus b_ad[34] ab9 io pci21lus pcib address/data bus b_ad[29] ab10 io pci21lus pcib address/data bus vdd ab11 b_ad[20] ab12 io pci21lus pcib address/data bus b_ad[10] ab13 io pci21lus pcib address/data bus b_ad[1] ab14 io pci21lus pcib address/data bus b_cbe_[0] ab15 io pci21lus pcib command/byte enable bus vdd ab16 b_par64 ab17 io pci21lus pcib ad[63:32]/cbe[7:4] even parity b_gnt_[2] ab18 o pci21lus pcib bus grant b_serr_ ab19 i pci21lis pcib system error vss ab20 a_req_[1] ab21 i pci21min pcia bus request vdd ab22 a_idsel[0] ab23 o pci21mun pcia con?g cycle chip selects a_idsel[1] ab24 o pci21mun pcia con?g cycle chip selects a_devsel_ ab25 io pcimxi21 pcia device select vdd ab26 b_ad[55] ac1 io pci21lus pcib address/data bus b_ad[57] ac2 io pci21lus pcib address/data bus b_ad[54] ac3 io pci21lus pcib address/data bus vss ac4 b_ad[40] ac5 io pci21lus pcib address/data bus b_ad[36] ac6 io pci21lus pcib address/data bus b_ad[31] ac7 io pci21lus pcib address/data bus b_ad[26] ac8 io pci21lus pcib address/data bus b_ad[22] ac9 io pci21lus pcib address/data bus b_ad[18] ac10 io pci21lus pcib address/data bus b_ad[15] ac11 io pci21lus pcib address/data bus b_ad[11] ac12 io pci21lus pcib address/data bus b_ad[6] ac13 io pci21lus pcib address/data bus b_ad[5] ac14 io pci21lus pcib address/data bus b_ad[0] ac15 io pci21lus pcib address/data bus b_cbe_[5] ac16 io pci21lus pcib command/byte enable bus table 3: pbga pinout (continued) signal name ball direction cell type description
20 STP2223BGA upa to pci interface u2p july 1997 b_cbe_[2] ac17 io pci21lus pcib command/byte enable bus b_req64_ ac18 io pci21lus pcib 64 bit request b_stop_ ac19 io pci21lus pcib stop b_gnt_[5] ac20 o pci21lus pcib bus grant b_gnt_[0] ac21 o pci21lus pcib bus grant b_req_[2] ac22 i pci21lis pcib bus request vss ac23 a_gnt_[0] ac24 o pci21mun pcia bus grant a_idsel[2] ac25 o pci21mun pcia con?g cycle chip selects a_perr_ ac26 io pcimxi21 pcia bus parity error b_ad[52] ad1 io pci21lus pcib address/data bus b_ad[53] ad2 io pci21lus pcib address/data bus b_ad[51] ad3 io pci21lus pcib address/data bus b_ad[45] ad4 io pci21lus pcib address/data bus b_ad[41] ad5 io pci21lus pcib address/data bus b_ad[38] ad6 io pci21lus pcib address/data bus b_ad[35] ad7 io pci21lus pcib address/data bus b_ad[30] ad8 io pci21lus pcib address/data bus b_ad[25] ad9 io pci21lus pcib address/data bus b_ad[21] ad10 io pci21lus pcib address/data bus b_ad[17] ad11 io pci21lus pcib address/data bus b_ad[14] ad12 io pci21lus pcib address/data bus b_ad[9] ad13 io pci21lus pcib address/data bus b_ad[2] ad14 io pci21lus pcib address/data bus b_cbe_[6] ad15 io pci21lus pcib command/byte enable bus b_cbe_[3] ad16 io pci21lus pcib command/byte enable bus b_ack64_ ad17 io pci21lus pcib 64bit ack b_irdy_ ad18 io pci21lus pcib initiator ready b_par ad19 io pci21lus pcib ad[31:0]/cbe[3:0] even parity b_gnt_[1] ad20 o pci21lus pcib bus grant b_req_[4] ad21 i pci21lis pcib bus request b_req_[1] ad22 i pci21lis pcib bus request a_clk ad23 i pci21min pcia bus clock phase detect (note 3) a_req_[2] ad24 i pci21min pcia bus request a_gnt_[1] ad25 o pci21mun pcia bus grant a_gnt_[2] ad26 o pci21mun pcia bus grant vss ae1 table 3: pbga pinout (continued) signal name ball direction cell type description
21 upa to pci interface u2p STP2223BGA july 1997 b_ad[48] ae2 io pci21lus pcib address/data bus b_ad[46] ae3 io pci21lus pcib address/data bus b_ad[42] ae4 io pci21lus pcib address/data bus b_ad[39] ae5 io pci21lus pcib address/data bus b_ad[37] ae6 io pci21lus pcib address/data bus b_ad[32] ae7 io pci21lus pcib address/data bus b_ad[27] ae8 io pci21lus pcib address/data bus b_ad[23] ae9 io pci21lus pcib address/data bus b_ad[19] ae10 io pci21lus pcib address/data bus b_ad[16] ae11 io pci21lus pcib address/data bus b_ad[12] ae12 io pci21lus pcib address/data bus b_ad[7] ae13 io pci21lus pcib address/data bus b_ad[4] ae14 io pci21lus pcib address/data bus vdd5 ae15 nvdd5p 5v input diode clamp reference voltage (note2) b_cbe_[4] ae16 io pci21lus pcib command/byte enable bus b_cbe_[1] ae17 io pci21lus pcib command/byte enable bus b_frame_ ae18 io pci21lus pcib frame b_devsel_ ae19 io pci21lus pcib device select b_gnt_[4] ae20 o pci21lus pcib bus grant b_req_[5] ae21 i pci21lis pcib bus request b_req_[3] ae22 i pci21lis pcib bus request b_req_[0] ae23 i pci21lis pcib bus request a_serr_ ae24 i pci21min pcia system error a_gnt_[3] ae25 o pci21mun pcia bus grant vss ae26 vdd af1 vss af2 b_ad[47] af3 io pci21lus pcib address/data bus b_ad[44] af4 io pci21lus pcib address/data bus vdd af5 vss af6 b_ad[33] af7 io pci21lus pcib address/data bus b_ad[28] af8 io pci21lus pcib address/data bus b_ad[24] af9 io pci21lus pcib address/data bus vdd af10 vss af11 b_ad[13] af12 io pci21lus pcib address/data bus table 3: pbga pinout (continued) signal name ball direction cell type description
22 STP2223BGA upa to pci interface u2p july 1997 (1) pcia vdd5 - for proper noise immunity, tie to 3.3v for pci cards which use 3v signalling, tie to 5v for pci cards which use 5v signalling. (2) misc vdd5 - tie to 5v. internal to u2p these three pins are part of a single voltage rail. (3) a_clk, b_clk - used by u2p to determine the clock phase of a given pcia, pcib cycle, respectively. required since either bu s can be running at half the frequency of the internal clock. input buffers u2p implements four types of input buffers: 1. ttl upa and jtag inputs 2. 5v tolerant ttl int_num and tmr_clk inputs 3. pci pci inputs (5v tolerant) 4. pecl upa_clk and upa_clk_l inputs note: refer to the lucent technologies hl350c 3 volt 0.35 micron. cmos standard-cell library data book for full specification on the buffer types. generally an input buffer is 5 volt tolerant if it is a pci buffer (and vdd5 is tied to 5 volts) or if it is of type b5xxxx. b_ad[8] af13 io pci21lus pcib address/data bus b_ad[3] af14 io pci21lus pcib address/data bus b_cbe_[7] af15 io pci21lus pcib command/byte enable bus vss af16 vdd af17 b_trdy_ af18 io pci21lus pcib target ready b_perr_ af19 io pci21lus pcib bus parity error b_gnt_[3] af20 o pci21lus pcib bus grant vss af21 vdd af22 b_clk af23 i pci21lis pcib bus clock phase detect (note 3) a_req_[3] af24 i pci21min pcia bus request vss af25 vdd af26 table 3: pbga pinout (continued) signal name ball direction cell type description
23 upa to pci interface u2p STP2223BGA july 1997 e lectrical s pecifications absolute maximum ratings stresses beyond those listed in the following table may cause physical damage to the device and should be avoided. (1) the 5v supply should be powered up before the 3v supply. in any case the 5v supply should never be more than 0.4v below the 3v supply. (2) except 5v tolerant pci buffers where vin max = vdd5 + 0.3v recommended operating conditions table 4: absolute maximum ratings symbol parameter limit unit vdd dc power supply voltage -0.5 to 5.0 (note 1) v vdd5 dc power supply voltage -0.5 to 7.0 (note 1) v vin, vout dc input, output voltage vss - 0.3 to vdd + 0.3 (note 2) v i dc current drain per vdd and vss pair 100 ma t stg storage temperature -40 to 125 c t cm maximum case temperature 85 c pd power dissipation 3.0 watts table 5: recommended operating conditions symbol parameter limit unit vdd dc power supply voltage 3.135 to 3.465 v vdd5 pci input reference voltage 4.75 to 5.25 when vdd5 = 5v 3.135 to 3.465 when vdd5 = 3.3v v vin, vout dc input, output voltage 0 to vdd v t co operating casetemperature 0 to 70 c
24 STP2223BGA upa to pci interface u2p july 1997 dc characteristics environmental electrical protection ac characteristics all upa inputs and outputs are referenced to the pecl clock input upa_sys_clk + and upa_sys_clk -. this clock input also controls an on-chip phase lock loop (pll). all upa inputs and outputs are clocked by the rising edge of clk + at the crossover between clk +and clk -, where both signals are at the same volt- age. all upa inputs are applied with a rise and fall time of 1.0 ns (nanosecond). pci inputs and outputs are referenced to pcia_clk and pcib_clk respectively. other u2p internal blocks run at the psyclops_clk, which is ?xed at 66.7 mhz (15ns). there is a synchro- nization boundary between the upa interface block and other internal blocks. table 6: dc characteristics symbol parameter conditions min max unit vil input low voltage ttl 0.8 v pci -0.3 0.3 vdd v pecl upa_clk, upa_clk_l vdd -1.475 vih input high voltage ttl 2.0 v pci 0.5vdd vdd +0.5 v pecl upa_clk, upa_clk_l vdd -1.165 vol output low voltage ttl iol = -4, -8, -16 ma 0.4 v pcia (dc) iol = 1.5 ma 0.1 vdd v pcib (dc) iol = 6.0 ma 0.55 v voh output high voltage ttl ioh = -4, -8, -16 ma 2.4 v pcia (dc) ioh = - 0.5 ma 0.9 vdd v pcib (dc) ioh = - 2.0 ma 2.4 v iin input leakage 1 m a ioz tri-state outputs voh = vss or vdd 9 m a cin input capacitance any input/bidir buffer 2.5 6 pf cout output capacitance any output buffer 2.5 6 pf table 7: environmental electrical protection esd latch up minimum minimum 2kv 150 ma
25 upa to pci interface u2p STP2223BGA july 1997 the jtag signals are referenced to jtag test clock psy_tclk. they are asynchronous signals with respect to upa and pci signals. the design of the u2p asic was done under the conditions speci?ed in table 8:. note: worst case slow motive claims operation of the two clock domains at the following max frequencies; upaclk = 105.9 mhz, psyclk = 67.5 mhz. pll clock distribution and characteristics figure 5. shows the pll scheme inside the u2p. figure 5. pll clock distribution circuitry . table 8: internal timing characteristics symbol parameter conditions min max unit upaclk operating frequency, upa_clk 3.15v, tj = 85c 100 mhz psyclk operating frequency, psyclops_clk 3.15v, tj = 85c 66 mhz clkskew internal skew and jitter - 0.5 0.5 ns table 9: pll characteristics symbol parameter conditions min max unit upaclk operating frequency, upa_clk 40 125 mhz psyclk operating frequency, psyclops_clk 40 85 mhz clkskew internal skew and jitter 125mhz 400 ps 100mhz 450 ps 66mhz 500 ps 35mhz 600 ps clk+ bied03t clkC pll1xsf n p z fbin fbout refclk fbclk1x clk1x bypass pll_bypass jtag_tck clock select from tap controller clock buffers internal clock clock mux
26 STP2223BGA upa to pci interface u2p july 1997 note: if the clock is stopped after the pll is locked and the feedback loop is not broken, the pll will go to the low frequency state, i.e., 4-10mhz. if the clock recovers and resumes normal operation the pll will catch up with the input clock within 250 m sec. note: if the feedback loop is broken and the input frequency is higher than the feedback frequency, there will be run-away i.e., pll will go to high frequency state. the only way to recover is to bring bypass up for 200 m sec. upa timing a timing diagram is shown in figure 6. as a reference for the data in the timing tables. upa input and output signals are referenced to the rising edge of upa_clktiming diagrams figure 6. timing waveforms clock t hc t lc t rc t fc clock input signal t su t h output signal t co 1.5v 1.5v 1.5v 1.5v 90% 10% t cycle parameter de?nitions t su : required setup time of a chip input referenced to a given (clock) edge. t h : required hold time of a chip input referenced to a given (clock) edge. t c o : guaranteed propagation time of an output referenced to a given (clock) edge. t v o : guaranteed output hold time of an output referenced to a given (clock) edge. t h c : required clock high time. t lc : required clock low time. t rc : required clock rise time. t fc : required clock fall time. t vo
27 upa to pci interface u2p STP2223BGA july 1997 the maximum skews between the rising edge and the falling edge of upa_clk + and upa_clk - are 50 ps. that is, the rising edge of upa_clk + can be shared at most 50 ps after/before the falling edge of upa_clk -. the falling edge of upa_clk + can be skewed at most 50 ps after/before the rising edge of upa_clk -. note: worst case slow motive shows tco_max = 4.1 ns @ 70 pf. table 10: upa_clk characteristics signal name description dc levels min max unit tcycle clock cycle time v il v dd - 1.165 4.4 ns t lc clock low time 4.4 ns t rc clock rise time 600 ps t fc clock fall time 600 ps table 11: upa input and output timing signal name description condition min max unit t su input setup time 2.1 ns t h input hold time 0.5 ns t co output propagation time 55pf 0 4.1 ns t vo output hold time 55pf 0.5 ns t ri input rise time 1.0 ns t fi input fall time 1.0 ns
28 STP2223BGA upa to pci interface u2p july 1997 pci timing figure 7. ac timing parameters t_su t_hold t_high t_high t_cyc t_val t_on t_off clock input output tri_output t_low
29 upa to pci interface u2p STP2223BGA july 1997 note: measurement conditions for tval (max) rise = 25 ohm/10pf parallel to ground, and for tval (max) fall = 10pf to ground, 25 ohm to vdd. refer to pci 2.1 speci?cation, chapter 7, for full ac speci?cations on output buffers. table 12: pcia ac timing characteristics symbol parameter conditions min max unit t_cyc pci_clk cycle time 15 30 ns t_high pci_clk high time 6 ns t_low pci_clk low time 6 ns pci inputs t_su input setup time to pci_clk - bused 5 ns t_su(ptp) input setup time to pci_clk - pci_req_ 5 ns t_hold input hold time from pci_clk 0 ns pci outputs @ 66 mhz t_val pci_clk to signal valid delay - bused (see note) 1 6 ns t_val(ptp) pci_clk to signal valid delay - pci_req_l (see note) 1 6 ns t_on float to active delay (see note) 1 ns t_off active to float delay 14 ns pci outputs @ 33 mhz t_val pci_clk to signal valid delay - bused (see note) 2 11 ns t_val(ptp) pci_clk to signal valid delay - pci_req_l (see note) 2 12 ns t_on float to active delay (see note) 2 ns t_off active to float delay 28 ns table 13: pcib ac timing characteristics symbol parameter conditions min max unit t_cyc pci_clk cycle time 30 dc ns t_high pci_clk high time 11 ns t_low pci_clk low time 11 ns pci inputs t_su input setup time to pci_clk - bused 7 ns t_su(ptp) input setup time to pci_clk - pci_req_ 12 ns t_hold input hold time from pci_clk 0 ns pci outputs t_val pci_clk to signal valid delay - bused (see note) 2 11 ns
30 STP2223BGA upa to pci interface u2p july 1997 note: measurement conditions for tval (max) rise = 25 ohm/10pf parallel to ground, and for tval (max) fall = 10pf to ground, 25 ohm to vdd. refer to pci 2.1 speci?cation, chapter 7, for full ac speci?cations on output buffers. a_clk, b_clk timing figure 8. a_clk, b_clk ac timing parameters jtag timing t_val(ptp) pci_clk to signal valid delay - pci_req_l (see note) 2 12 ns t_on float to active delay (see note) 2 ns t_off active to float delay 28 ns table 14: a_clk, b_clk timing parameters symbol parameter conditions min max unit t_cyc psyclops_clk cycle time 15 25 ns t_skew clock skew to psyclops_clk -750 +750 ps t_duty a_clk, b_clk duty cycle requirement tcyc/2 -750 tcyc/2 +750 ps table 15: jtag timing characteristics symbol parameter conditions min max unit jtag clock t_cyc jtag clk cycle time 100 ns jtag inputs table 13: pcib ac timing characteristics (continued) symbol parameter conditions min max unit t_cyc psyclops_clk a_clk b_clk t_duty t_skew
31 upa to pci interface u2p STP2223BGA july 1997 m echanical i nformation package marking (production version) thermal data and characteristics (1) 0 lfm, no heatsink, 4w thermal die, 20 c ambient, sea level (2) 100 lfm, no heatsink, 4w thermal die, 20 c ambient, sea level t_su(rx) jtag inputs setup time to jtag_clk 30 ns t_hld(rx) jtag inputs hold time to jtag_clk 20 ns t_val jtag output valid time from jtag_clk negative edge 30pf load 49 ns yyww year and work week l assembly site xxxx wafer lot kn clean room number # chip version table 16: thermal characteristics package type theta_ja theta_jc unit 456 pbga/4 layers 12.8 (1) 3.7 c/w 11.8 (2) table 15: jtag timing characteristics (continued) symbol parameter conditions min max unit sun part number 100-4611-05 yywwl xxxxkn# (sun logo) sun STP2223BGA lucent technologies m-1298b5
32 STP2223BGA upa to pci interface u2p july 1997 package drawing 35.00 0.20 0.56 0.04 25 spaces @ 1.27 = 31.75 0.60 0.10 30.00 +0.70 -0.00 22.00 ref. all measurements in millimeters a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? ????????????????????? ? ? ??? solder ball grid array coordinates are for reference only a1 indicator (under cover coat) 1.63 typ 0.75 0.15 dia typ after reflow 25 spaces @ 1.27 = 31.75 1 3 5 7 9 1113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af square square 30 approx all sides 1.63 typ approx typ 4 places 17.50 0.20 a1 indicator (gold plated) solder ball grid array coordinates are for reference only see note 2 2.33 0.19 top view bottom view d 0.19 c seating plane see note 1 typ c 1.73 0.09 // 0.15 c notes: 1. seating plane is best fit plane as determined by coplanarity measurement equipment. 2. the flatness of the overmold surface in the center 12 x 12 mm area shall be within 0.13 mm.
33 upa to pci interface u2p STP2223BGA july 1997 o rdering i nformation document part number: 802-7834-02 part number speed description STP2223BGA upa to pci interface
34 STP2223BGA upa to pci interface u2p july 1997

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